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19-3256; Rev 0; 4/04
Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load
General Description
The MAX9961/MAX9962 dual, low-power, high-speed, pin electronics driver/comparator/load (DCL) ICs include, for each channel, a three-level pin driver, a dual comparator, variable clamps, and an active load. The driver features a wide voltage range and highspeed operation, includes high-impedance and activetermination (3rd-level drive) modes, and is highly linear even at low voltage swings. The dual comparator provides low dispersion (timing variation) over a wide variety of input conditions. The clamps provide damping of high-speed device-under-test (DUT) waveforms when the device is configured as a high-impedance receiver. The programmable load supplies up to 2mA of source and sink current. The load facilitates contact/continuity testing and pullup of high-output-impedance devices. The MAX9961A/MAX9962A provide tight matching of offset for the drivers and the comparators, allowing reference levels to be shared across multiple channels in cost-sensitive systems. Use the MAX9961B/MAX9962B for system designs that incorporate independent reference levels for each channel. The MAX9961/MAX9962 provide high-speed, differential control inputs compatible with LVPECL, LVDS, and GTL. The MAX9961/MAX9962 are available with optional internal termination resistors. The open-collector comparator outputs are available with or without internal pullup resistors. The optional internal resistors significantly reduce the discrete component count on the circuit board. A 3-wire, low-voltage, CMOS-compatible serial interface programs the low-leakage, slew-rate limit, and tri-state/ terminate operational configurations of the MAX9961/ MAX9962. The MAX9961/MAX9962s' operating range is -1.5V to +6.5V with power dissipation of only 900mW per channel. The devices are available in a 100-pin, 14mm x 14mm body, and 0.5mm pitch TQFP. An exposed 8mm x 8mm die pad on the top (MAX9961) or bottom (MAX9962) of the package facilitates efficient heat removal. The device is specified to operate with an internal die temperature of +70C to +100C, and features a die temperature monitor output.
Features
Low Power Dissipation: 900mW/Channel (typ) High Speed: 500Mbps at 3VP-P Programmable 2mA Active-Load Current Low Timing Dispersion Wide -1.5V to +6.5V Operating Range Active Termination (3rd-Level Drive) Low-Leakage Mode: 15nA (max) Integrated Clamps Interface Easily with Most Logic Families
MAX9961/MAX9962
Integrated PMU Connection Digitally Programmable Slew Rate Internal Termination Resistors Low Offset Error
Ordering Information
PART MAX9961ADCCQ MAX9961AGCCQ* MAX9961ALCCQ MAX9961BDCCQ MAX9961BGCCQ* MAX9961BLCCQ MAX9962ADCCQ* MAX9962AGCCQ* MAX9962ALCCQ* MAX9962BDCCQ* MAX9962BGCCQ* MAX9962BLCCQ* TEMP RANGE 0oC to +70oC 0oC to +70oC 0 C to +70 C 0oC to +70oC 0oC to +70oC 0 C to +70 C 0oC to +70oC 0oC to +70oC 0 C to +70 C 0oC to +70oC 0 C to +70 C 0oC to +70oC
o o o o o o o o
PIN-PACKAGE** 100 TQFP-EPR 100 TQFP-EPR 100 TQFP-EPR 100 TQFP-EPR 100 TQFP-EPR 100 TQFP-EPR 100 TQFP-EP 100 TQFP-EP 100 TQFP-EP 100 TQFP-EP 100 TQFP-EP 100 TQFP-EP
*Future product--contact factory for availability. **EPR = Exposed pad reversed (top), EP = exposed pad (bottom).
Applications
Low-Cost Mixed-Signal/System-on-Chip ATE Commodity Memory ATE PCI or VXI Programmable Digital Instruments
Pin Configurations appear at end of data sheet. Selector Guide appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
ABSOLUTE MAXIMUM RATINGS
VCC to GND .........................................................-0.3V to +11.5V VEE to GND............................................................-7.0V to +0.3V VCC - VEE ................................................................-0.3V to +18V GS to GND .............................................................................1V DATA_, NDATA_, RCV_, NRCV_, LDEN_, NLDEN_ to GND................................................-2.5V to +5.0V DATA_ to NDATA_, RCV_ to NRCV_, LDEN_ to NLDEN_.....1.5V VCCO_ to GND ..........................................................-0.3V to +5V SCLK, DIN, CS, RST, TDATA_, TRCV_, TLDEN_ to GND ...................................................-1.0V to +5V DHV_, DLV_, DTV_, CHV_, CLV_, COM_, FORCE_, SENSE_ to GND.................................-2.5V to +7.5V DUT_, LDH_, LDL_ to GND ...................................-2.5V to +7.5V CPHV_ to GND ......................................................-2.5V to +8.5V CPLV_ to GND.......................................................-3.5V to +7.5V DHV_ to DLV_ ......................................................................10V DHV_ to DTV_ ......................................................................10V DLV_ to DTV_.......................................................................10V CHV_ or CLV_ to DUT_ ........................................................10V CH_, NCH_, CL_, NCL_ to GND...............................-2.5V to +5V All Other Pins to GND .......................(VEE - 0.3V) to (VCC + 0.3V) DHV_, DLV_, DTV_, CHV_, CLV_, CPHV_, CPLV_ Current ...10mA TEMP Current...................................................-0.5mA to +20mA DUT_ Short Circuit to -1.5V to +6.5V..........................Continuous Power Dissipation (TA = +70C) MAX9961_ _CCQ (derate 167mW/C above +70C) ...13.3W* MAX9962_ _CCQ (derate 45.5mW/C above +70C) ....3.6W* Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+125C Lead Temperature (soldering, 10s) .................................+300C
*Dissipation wattage values are based on still air with no heat sink for the MAX9961 and slug soldered to board copper for the MAX9962. Actual maximum allowable power dissipation is a function of heat extraction technique and may be substantially higher.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85C, unless otherwise noted. All temperature coefficients are measured at TJ = +70C to +100C, unless otherwise noted.) (Note 1)
PARAMETER POWER SUPPLIES Positive Supply Negative Supply Positive Supply Current (Note 2) Negative Supply Current (Note 2) Power Dissipation DUT_ CHARACTERISTICS Operating Voltage Range Leakage Current in High-Impedance Mode VDUT IDUT (Note 4) LLEAK = 0, 0 VDUT_ 3V LLEAK = 0, VDUT_ = -1.5V, +6.5V LLEAK = 1; VDUT_ = -1.5V, 0, +3V; VLDH_ = VLDL_ = 0, 5V; TJ < +90C LLEAK = 1, VDUT_ = 6.5V, TJ < +90C, VCHV_ = VCLV_ = 6.5V, VLDH_ = VLDL_ = 0, 5V CDUT Driver in term mode (DUT_ = DTV_) Driver in high-impedance mode (Notes 5, 7) 1 5 20 -1.5 +6.5 1.5 3 15 nA 30 pF s V A VCC VEE ICC IEE PD VLDH_ = VLDL_ = 0 VLDH_ = VLDL_ = 5V VLDH_ = VLDL_ = 0 VLDH_ = VLDL_ = 5V (Notes 2, 3) 9.5 -6.5 9.75 -5.25 90 100 -180 -190 1.8 10.5 -4.5 110 120 -200 -210 2.1 V V mA mA W SYMBOL CONDITIONS MIN TYP MAX UNITS
Leakage Current in Low-Leakage Mode
Combined Capacitance Low-Leakage Enable Time
2
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85C, unless otherwise noted. All temperature coefficients are measured at TJ = +70C to +100C, unless otherwise noted.) (Note 1)
PARAMETER Low-Leakage Disable Time Low-Leakage Recovery SYMBOL (Notes 6, 7) Time to return to the specified maximum leakage after a 3V, 4V/ns step at DUT_ (Note 7) CONDITIONS MIN TYP 20 15 MAX UNITS s s
MAX9961/MAX9962
LEVEL PROGRAMMING INPUTS (DHV_, DLV_, DTV_, CHV_, CLV_, CPHV_, CPLV_, COM_, LDH_, LDL_) Input Bias Current Settling Time Input High Voltage Input Low Voltage Differential Input Voltage Input Bias Current Input Termination Voltage VTDATA_ VTRCV_ VTLDEN_ VIH VIL VDIFF MAX996_ _DCCQ, MAX996_ _GCCQ, MAX996_ _LCCQ -0.2 IBIAS To 0.1% of full-scale change (Note 7) 0.85 -0.20 0.15 1 3.50 +3.10 1.00 25 +3.5 25 A s V V V A V
DIFFERENTIAL CONTROL INPUTS (DATA_, NDATA_, RCV_, NRCV_, LDEN_, NLDEN_)
Input Termination Resistor
MAX996_ _GCCQ, MAX996_ _LCCQ, between signal and corresponding termination voltage input
48
52
SINGLE-ENDED CONTROL INPUTS (CS, SCLK, DIN, RST) Internal Threshold Reference Internal Reference Output Resistance External Threshold Reference Input High Voltage Input Low Voltage Input Bias Current SERIAL INTERFACE TIMING (Figure 4) SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Low to SCLK High Setup CS High to SCLK High Setup SCLK High to CS High Hold DIN to SCLK High Setup DIN to SCLK High Hold CS Pulse-Width High fSCLK tCH tCL tCSS0 tCSS1 tCSH1 tDS tDH tCSWH 8 8 3.5 3.5 3.5 3.5 3.5 20 50 MHz ns ns ns ns ns ns ns ns VTHRINT RO VTHR VIH VIL IB 0.43 VTHR + 0.20 -0.1 1.05 1.25 20 1.73 3.5 VTHR 0.20 25 1.45 V k V V V A
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85C, unless otherwise noted. All temperature coefficients are measured at TJ = +70C to +100C, unless otherwise noted.) (Note 1)
PARAMETER TEMPERATURE MONITOR (TEMP) Nominal Voltage Temperature Coefficient Output Resistance DRIVERS (Note 8) DC OUTPUT CHARACTERISTICS (RL 10M) DHV_, DLV_, DTV_ Output Offset Voltage DHV_, DLV_, DTV_ Output-Offset Temperature Coefficient DHV_, DLV_, DTV_ Gain DHV_, DLV_, DTV_ Gain Temperature Coefficient Linearity Error DHV_ to DLV_ Crosstalk DLV_ to DHV_ Crosstalk DTV_ to DLV_ and DHV_ Crosstalk DHV_ to DTV_ Crosstalk DLV_ to DTV_ Crosstalk DHV_, DTV_, DLV_ DC PowerSupply Rejection Ratio Maximum DC Drive Current DC Output Resistance DC Output Resistance Variation Sense Resistance Force Resistance Force Capacitance PSRR IDUT_ RDUT_ RDUT_ RSENSE RFORCE CFORCE VDLV_ = 0, VDHV_ = 0.1V Drive-Mode Overshoot Term-Mode Overshoot VDLV_ = 0, VDHV_ = 1V VDLV_ = 0, VDHV_ = 3V (Note 13) IDUT_ = 30mA (Note 12) IDUT_ = 1mA to 8mA IDUT_ = 1mA to 40mA 7.50 320 VDUT_ = 1.5V, 3V (Note 9) Full range (Notes 9, 10) VDLV_ = 0, VDHV_ = 200mV, 6.5V VDHV_ = 5V, VDLV_ = -1.5V, +4.8V VDHV_ = 3V, VDLV_ = 0, VDTV_ = -1.5V, +6.5V VDTV_ = 1.5V, VDLV_ = 0, VDHV_ = 1.6V, 3V VDTV_ = 1.5V, VDHV_ = 3V, VDLV_ = 0V, 1.4V (Note 11) 40 60 49 50 0.5 1 10 400 1 30 40 50 0 mV mV 2.5 13.75 500 120 51 Av Measured with VDHV_, VDLV_, and VDTV_ at 0 and 4.5V 0.960 -35 5 15 2 2 2 3 3 VOS At DUT_ with VDHV_, VDTV_, VDLV_ independently tested at +1.5V MAX996_A MAX996_B 65 1.001 15 mV 100 V/C V/V ppm/C mV mV mV mV mV mV dB mA k pF TJ = +70C, RL 10M 3.43 +10 15 V mV/C k SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC OUTPUT CHARACTERISTICS (ZL = 50)
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85C, unless otherwise noted. All temperature coefficients are measured at TJ = +70C to +100C, unless otherwise noted.) (Note 1)
PARAMETER Settling Time to Within 25mV Settling Time to Within 5mV Prop Delay, Data to Output Prop Delay Match, tLH vs. tHL Prop Delay Match, Drivers Within Package Prop Delay Temperature Coefficient Prop Delay Change vs. Pulse Width Prop Delay Change vs. Common-Mode Voltage Prop Delay, Drive to High Impedance Prop Delay, High Impedance to Drive Prop Delay, Drive to Term Prop Delay, Term to Drive tPDDZ tPDZD tPDDT tPDTD 3VP-P, 40MHz, 2.5ns to 22.5ns pulse width, relative to 12.5ns pulse width VDHV_ - VDLV_ = 1V, VDHV_ = 0 to 6V VDHV_ = 1.0V, VDLV_ = -1.0V, VDTV_ = 0 VDHV_ = 1.0V, VDLV_ = -1.0V, VDTV_ = 0 VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V 0.2VP-P, 20% to 80% Rise and Fall Time tR, tF 1VP-P, 10% to 90% 3VP-P, 10% to 90% 5VP-P, 10% to 90% Rise- and Fall-Time Match SC1 = 0, SC0 = 1 Slew Rate SC1 = 1, SC0 = 0 Slew Rate SC1 = 1, SC0 = 1 Slew Rate tR vs. tF 3VP-P, 10% to 90% Percent of full speed (SC0 = SC1 = 0), 3VP-P, 20% to 80% Percent of full speed (SC0 = SC1 = 0), 3VP-P, 20% to 80% Percent of full speed (SC0 = SC1 = 0), 3VP-P, 20% to 80% 0.2VP-P Minimum Pulse Width (Note 17) 1VP-P 3VP-P 5VP-P 0.2VP-P Data Rate (Note 18) 1VP-P 3VP-P 5VP-P 1.0 tPDD 3VP-P (Note 16) SYMBOL CONDITIONS 3V step (Note 14) 3V step (Note 14) MIN TYP 10 20 2.2 50 40 +3 60 85 3.1 3.2 2.4 2.1 0.37 0.63 1.2 2.0 0.03 75 50 25 0.65 1.0 2.0 2.9 1700 1000 500 350 Mbps ns ns % % % 1.5 ns MAX UNITS ns ns ns ps ps ps/C ps ps ns ns ns ns
MAX9961/MAX9962
TIMING CHARACTERISTICS (ZL = 50) (Note 15)
DYNAMIC PERFORMANCE (ZL = 50)
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85C, unless otherwise noted. All temperature coefficients are measured at TJ = +70C to +100C, unless otherwise noted.) (Note 1)
PARAMETER Dynamic Crosstalk Rise and Fall Time, Drive to Term tDTR, tDTF SYMBOL (Note 19) VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, 10% to 90%, Figure 1a (Note 20) VDHV_ = 3V, VDLV_ = 0, VDTV_ = 1.5V, 10% to 90%, Figure 1b (Note 20) CONDITIONS MIN TYP 10 1.6 MAX UNITS mVP-P ns
Rise and Fall Time, Term to Drive COMPARATORS (Note 8) DC CHARACTERISTICS Input Voltage Range Differential Input Voltage Hysteresis Input Offset Voltage Input-Offset-Voltage Temperature Coefficient Common-Mode Rejection Ratio (Note 21)
tTDR, tTDF
0.7
ns
VIN VDIFF VHYST VOS
(Note 4)
-1.5 8 0 MAX996_A MAX996_B 50
+6.5
V V mV
VDUT_ = 1.5V
20 100
mV V/C
VDUT_ = 0, 3V CMRR VDUT_ = 0, 6.5V VDUT_ = -1.5, +6.5V VDUT_ = 1.5V, 3V
47 54 44
78 78 61 3 5 25 mV dB
Linearity Error (Note 9) VCC Power-Supply Rejection Ratio (Note 11) VEE Power-Supply Rejection Ratio (Note 11) AC CHARACTERISTICS (Note 22) Minimum Pulse Width Prop Delay Prop Delay Temperature Coefficient Prop Delay Match, High/Low vs. Low/High Prop Delay Match, Comparators Within Package Prop Delay Dispersion vs. Common-Mode Input (Note 24) Prop Delay Dispersion vs. Overdrive tPW(MIN) tPDL
VDUT_ = 6.5V VDUT_ = -1.5V PSRR PSRR VDUT_ = -1.5V, +6.5V VDUT_ = 0, 6.5V VDUT_ = -1.5V (Note 23) 57 44 33 80 64 60 0.7 2.2 +6 25 (Note 16) VCHV_ = VCLV_ = 0, 6.4V VCHV_ = VCLV_ = -1.4V 100mV to 1V 35 75 175 220
dB dB
ns ns ps/C ps ps ps ps
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85C, unless otherwise noted. All temperature coefficients are measured at TJ = +70C to +100C, unless otherwise noted.) (Note 1)
PARAMETER Prop Delay Dispersion vs. Pulse Width Prop Delay Dispersion vs. Slew Rate Waveform Tracking 10% to 90% LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_) VCCO_ Voltage Range Output Low-Voltage Compliance Output High Current Output Low Current Output High Voltage Output Low Voltage Output Voltage Swing Output Termination Resistor RTERM IOH IOL VOH VOL VVCCO_ Set by IOL, RTERM, and VCCO_ MAX996_ _DCCQ, MAX996_ _GCCQ MAX996_ _DCCQ, MAX996_ _GCCQ ICH_ = INCH_ = ICL_ = INCL_ = 0, MAX996_ _LCCQ ICH_ = INCH_ = ICL_ = INCL_ = 0, MAX996_ _LCCQ ICH_ = INCH_ = ICL_ = INCL_ = 0, MAX996_ _LCCQ Single-ended measurement from VCCO_ to CH_, NCH_, CL_, NCL_, MAX996_ _LCCQ MAX996_ _DCCQ, MAX996_ _GCCQ, RTERM = 50 at end of line MAX996_ _LCCQ MAX996_ _DCCQ, MAX996_ _GCCQ, RTERM = 50 at end of line MAX996_ _LCCQ CLAMPS High-Clamp Input Voltage Range Low-Clamp Input Voltage Range Clamp Offset Voltage Offset-Voltage Temperature Coefficient Clamp Power-Supply Rejection Ratio (Note 11) Voltage Gain PSRR AV IDUT_ = 1mA, VCPHV_ = 0 IDUT_ = -1mA, VCPLV_ = 0 0.96 VCPH_ VCPL_ VOS At DUT_ with IDUT_ = 1mA, VCPHV_ = 0 At DUT_ with IDUT_ = -1mA, VCPLV_ = 0 0.5 54 54 1.00 -0.3 -2.5 +7.5 +5.3 100 100 V V mV mV/C dB V/V 360 48 -0.05 7.6 0 -0.5 0 8 +0.10 8.4 3.5 V V mA mA V V 440 52 mV SYMBOL CONDITIONS 2.5ns to 22.5ns pulse width, relative to 12.5ns pulse width 0.5V/ns to 2V/ns slew rate VDUT_ = 1.0VP-P, tR = tF = Term mode 1.0ns, 10% to 90% relative High-impedance to timing at 50% point mode MIN TYP 40 100 250 ps 500 MAX UNITS ps ps
MAX9961/MAX9962
VCCO - VCCO_ 0.05 0.005 VCCO_ 0.4 390
Differential Rise Time
tR
20% to 80%
280 280 280 280
ps
Differential Fall Time
tF
20% to 80%
ps
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85C, unless otherwise noted. All temperature coefficients are measured at TJ = +70C to +100C, unless otherwise noted.) (Note 1)
PARAMETER Voltage-Gain Temperature Coefficient IDUT_ = 1mA, VCPLV_ = -1.5V, VCPHV_ = -0.3V to +6.5V IDUT_ = -1mA, VCPHV_ = 6.5V, VCPLV_ = -1.5V to +5.3V VCPLV_ = -1.5V, VCPHV_ = 0, VDUT_ = 6.5V VCPLV_ = 5V, VCPHV_ = 6.5V, VDUT_ = -1.5V VCPHV_ = 3V, VCPLV_ = 0, IDUT_ = 5mA and 15mA 50 -95 50 SYMBOL CONDITIONS MIN TYP -100 10 mV 10 95 mA -50 55 MAX UNITS ppm/C
Clamp Linearity
Short-Circuit Output Current
ISCDUT_
Clamp DC Impedance
ROUT
ACTIVE LOAD (Driver in high-impedance mode, unless otherwise noted.) COMMUTATION AMPLIFIER (VCOM_ = +2.5V, ISOURCE = ISINK = 2mA, RL > 1M) COM_ Voltage Range COM_ Offset Voltage Offset-Voltage Temperature Coefficient COM_ Voltage Gain Voltage-Gain Temperature Coefficient COM_ Linearity Error COM_ Output Voltage PowerSupply Rejection Ratio Differential Voltage Range Output Resistance, Sink or Source Output Resistance, Linear Region Deadband Maximum Source Current Source Programming Gain Source Current Offset (Combined Offset of LDL_ and GS) Source-Current Temperature Coefficient ATC IOS Ro Ro PSRR VCOM_ = -1.5V, +5.7V (Note 9) 40 AV VCOM_ = 0, 4.5V 0.98 -20 2 15 VCOM_ Vos 100 1.00 -1.5 +5.7 100 V mV V/C V/V ppm/C mV dB
OUTPUT CHARACTERISTICS (ISOURCE = ISINK = 2mA, RL > 1M) VDUT__- VCOM_ VDUT_ = 4.5V, 6.5V with VCOM_ = -1.5V, and VDUT_ = -1.5V, +0.5V with VCOM_ = 5.7V IDUT_ = 1mA, VCOM_ = +2.5V 95% ISOURCE to 95% ISINK, VCOM_ = +2.5V VLDL_ = 5.5V VLDL_ = 1.25V, 5V VLDL_ = 20mV VLDL_ = 100mV VLDL_ = 5V 2.1 392 -5 -0.02 -0.3 -7.2 200 500 60 310 2.2 400 450 2.3 408 +10 +8.0 V k mV mA A/V A A/C
SOURCE CURRENT (VDUT_ = +5V, VCOM_ = +2.5V)
8
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85C, unless otherwise noted. All temperature coefficients are measured at TJ = +70C to +100C, unless otherwise noted.) (Note 1)
PARAMETER Source-Current Power-Supply Rejection Ratio Source-Current Linearity (Note 25) SINK CURRENT (VDUT_ = 0, VCOM_ = +2.5V) Maximum Sink Current Sink Programming Gain Sink Current Offset (Combined Offset of LDH_ and GS) Sink-Current Temperature Coefficient Sink-Current Power-Supply Rejection Ratio Sink-Current Linearity GROUND SENSE (GS) Voltage Range VGS Verified by GS common-mode error test VDUT_ = 0, VCOM_ = +2.5V, VGS = 250mV, VLDH_ - VGS = 2.5V VDUT_ = 5V, VCOM_ = +2.5V, VGS = 250mV, VLDL_ - VGS = 2.5V Input Bias Current AC CHARACTERISTICS (ZL = 50 to GND) Enable Time (Note 26) Disable Time (Note 26) Current Settling Time on Commutation Spike During Enable/Disable Transition tEN tDIS ISOURCE = 2mA, VCOM_ = -1.5V ISINK = 2mA, VCOM_ = +1.5V ISOURCE = 2mA, VCOM_ = -1.5V ISINK = 2mA, VCOM_ = +1.5V ISOURCE = ISINK = 500A (Notes 7 and 27) To 10% To 1% 2.5 2.2 1.7 1.7 0.4 1.1 30 ns ns ns mV VGS = 0 250 5 A 5 25 A mV PSRR ATC IOS VLDH_ = 5.5V VLDH_ = 1.25V to 5V VLDH_ = 20mV VLDH_ = 100mV VLDH_ = 5V VLDH_ = 100mV VLDH_ = 5V VLDH_ = 100mV, 1.25V, 5V (Note 25) -2.3 -408 -10 +0.05 +0.4 1.3 3.7 10 4 100 25 -2.2 -400 -2.1 -392 +5 mA mA/V A A/C A/V A SYMBOL PSRR VLDL_ = 5V VLDL_ = 100mV, 1.25V, 5V CONDITIONS VLDL_ = 100mV MIN TYP 0.7 3 2 MAX 4 100 10 UNITS A/V A
MAX9961/MAX9962
Common-Mode Error
ISOURCE = ISINK = 2mA, VCOM_ = 0
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
All minimum and maximum limits are 100% production tested. Tests are performed at nominal supply voltages unless otherwise noted. Total for dual device at worst-case setting; driver enabled and load disabled. RL 10M. The supply currents are measured with typical supply voltages. Does not include internal dissipation of the comparator outputs. For MAX996_ _LCCQ, additional power dissipation is typically (32mA) x (VVCCO). Externally forced voltages can exceed this range provided that the Absolute Maximum Ratings are not exceeded. Transition time from LLEAK being asserted to leakage current dropping below specified limits. Transition time from LLEAK being deasserted to output returning to normal operating mode. Based on simulation results only. With the exception of Offset and Gain/CMRR tests, reference input values are calibrated for offset and gain. Relative to straight line between 0 and 4.5V. _______________________________________________________________________________________ 9
Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +9.75V, VEE = -5.25V, VCCO_ = +2.5V, SC1 = SC0 = 0, VCPHV_ = +7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VGS = 0, TJ = +85C, unless otherwise noted. All temperature coefficients are measured at TJ = +70C to +100C, unless otherwise noted.) (Note 1) Note 10: Specifications measured at the end points of the full range. Full ranges are -1.3V VDHV_ +6.5V, -1.5V VDLV_ +6.3V, -1.5V VDTV_ +6.5V. Note 11: Change in offset voltage with power supplies independently set to their minimum and maximum values. Note 12: Nominal target value is 50. Contact factory for alternate trim selections within the 45 to 51 range. Note 13: VDTV_ = +1.5V, RS = 50. External signal driven into T-line is a 0 to +3V edge with 1.2ns rise time (10% to 90%). Measurement is made using the comparator. Note 14: Measured from the crossing point of DATA_ inputs to the settling of the driver output. Note 15: Prop delays are measured from the crossing point of the differential input signals to the 50% point of the expected output swing. Rise time of the differential inputs DATA_ and RCV_ is 250ps (10% to 90%). Note 16: Rising edge to rising edge or falling edge to falling edge. Note 17: Specified amplitude is programmed. At this pulse width, the output reaches at least 95% of its nominal (DC) amplitude. The pulse width is measured at DATA_. Note 18: Specified amplitude is programmed. Maximum data rate is specified in transitions per second. A square wave that reaches at least 95% of its programmed amplitude may be generated at one-half this frequency. Note 19: Crosstalk from either driver to the other. Aggressor channel is driving 3VP-P into a 50 load. Victim channel is in term mode with VDTV_ = +1.5V. Note 20: Indicative of switching speed from DHV_ or DLV_ to DTV_ and DTV_ to DHV_ or DLV_ when VDLV_ < VDTV_ < VDHV_. If VDTV_ < VDLV_ or VDTV_ > VDHV_, switching speed is degraded by a factor of approximately 3. Note 21: Change in offset voltage over the input range. Note 22: Unless otherwise noted, all propagation delays are measured at 40MHz, VDUT_ = 0 to +2V, VCHV_ = VCLV_ = +1V, slew rate = 2V/ns, ZS = 50, driver in term mode with VDTV_ = 0. Comparator outputs are terminated with 50 to GND at scope input with VCCO_ = 2V. Open-collector outputs are also terminated (internally or externally) with RTERM = 50 to VCCO_. Measured from VDUT_ crossing calibrated CHV_ / CLV_ threshold to crossing point of differential outputs. Note 23: VDUT_ = 0 to +1V, VCHV_ = VCLV _ = +0.5V. At this pulse width, the output reaches at least 90% of its DC voltage swing. The pulse width is measured at the crossing points of the differential outputs. Note 24: Relative to propagation delay at VCHV_ = VCLV_ = +1.5V. VDUT_ = 200mVP-P. Overdrive = 100mV. Note 25: Relative to straight line between 0.5V and 2.5V. Note 26: Measured from crossing of input signals to the 10% point of the output voltage change. Note 27: VCOM_ = 1.5V, ZS = 50, driving voltage = 3V to 0 transition and 0 to 3V transition. Settling time is measured from VDUT_ = 1.5V to ISINK or ISOURCE settling within specified tolerance.
Typical Operating Characteristics
DRIVER SMALL-SIGNAL RESPONSE
MAX9961/62 toc01
DRIVER LARGE-SIGNAL RESPONSE
VDLV_ = 0 RL = 50 VDUT_ = 500mV/div
MAX9961/62 toc02
DRIVER TRAILING-EDGE TIMING ERROR vs. PULSE WIDTH
MAX9961/62 toc03
40 20 TIMING ERROR (ps) 0 -20 -40 -60 -80 NORMALIZED TO PW = 12.5ns PERIOD = 25ns, VDHV_ = 3V, VDLV_ = 0 0 5 10 15 20 HIGH PULSE LOW PULSE
VDLV_ = 0 RL = 50
VDHV_ = 500mV
VDUT_ = 50mV/div
VDHV_ = 200mV
VDHV_ = 5V
VDHV_ = 3V
0
VDHV_ = 100mV t = 2.50ns/div
0
VDHV_ = 1V -100 t = 2.50ns/div
25
PULSE WIDTH (ns)
10
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
Typical Operating Characteristics (continued)
DRIVER TIME DELAY vs. COMMON-MODE VOLTAGE
MAx9961/62 toc04
DRIVE-TO-TERM TRANSITION
MAX9961/62 toc05
HIGH-IMPEDANCE-TO-DRIVE TRANSITION
HIGH IMPEDANCE TO DHV_
MAX9961/62 toc06
60 50 40 TIME DELAY (ps) 30 20 10 0 -10 -20 -30 -0.5 NORMALIZED TO VCM = 1.5V 0.5 1.5 2.5 3.5 4.5 FALLING EDGE RISING EDGE
DHV_ TO DTV_
VDUT_ = 250mV/div
VDUT_ = 250mV/div DLV_ TO DTV_
0
0 RL = 50 5.5 t = 2.5ns/div
HIGH IMPEDANCE TO DLV_ RL = 50 t = 2.5ns/div
COMMON-MODE VOLTAGE (V)
DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE
6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 VDUT_ (V) VDUT_ = VDHV_ 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6
MAX9961/62 toc07
DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE
VDUT_ = VDLV_ 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
MAX9961/62 toc08
DRIVER LINEARITY ERROR vs. OUTPUT VOLTAGE
VDUT_ = VDTV_
MAX9961/62 toc09
LINEARITY ERROR (mV)
LINEARITY ERROR (mV)
LINEARITY ERROR (mV)
-1.5 -0.5 0.5
1.5
2.5
3.5
4.5
5.5
6.5
VDUT_ (V)
VDUT_ (V)
CROSSTALK TO DUT_ FROM DLV_ WITH DUT_ = DHV_
MAX9961/62 toc10
CROSSTALK TO DUT_ FROM DHV_ WITH DUT_ = DLV_
MAX9961/62 toc11
CROSSTALK TO DUT_ FROM DTV_ WITH DUT_ = DHV_
0.4 0.3 VDUT_ ERROR (mV) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 VDHV_ = 3V VDLV_ = 0
MAX9961/62 toc12
2.0 1.6 1.2 VDUT_ ERROR (mV) 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 -2.0 NORMALIZED AT VDLV_ = 0 -1.5 0 1.5 3.0 4.5 VDHV_ = 5V VDTV_ = 1.5V
2.0 1.6 1.2 VDUT_ ERROR (mV) 0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 -2.0 NORMALIZED AT VDHV_ = 5V -0.5 0.5 1.5 2.5 3.5 4.5 5.5 VDLV_ = 0 VDTV_ = 1.5V
0.5
-0.5 -1.5 -0.5 0.5
NORMALIZED AT VDTV_ = 1.5V 1.5 2.5 3.5 4.5 5.5 6.5 VDTV_ (V)
6.0
6.5
VDLV_ (V)
VDHV_ (V)
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11
Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
Typical Operating Characteristics (continued)
CROSSTALK TO DUT_ FROM DTV_ WITH DUT_ = DLV_
MAX9961/62 toc13
CROSSTALK TO DUT_ FROM DLV_ WITH DUT_ = DTV_
MAX9961/62 toc14
CROSSTALK TO DUT_ FROM DHV_ WITH DUT_ = DTV_
1.5 1.0 VDUT_ ERROR (mV) 0.5 0 -0.5 -1.0 -1.5 VDTV_ = 1.5V VDLV_ = -1.5V
MAX9961/62 toc15
0.5 0.4 0.3 VDUT_ ERROR (mV) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -1.5 -0.5 0.5 NORMALIZED AT VDTV_ = 1.5V 1.5 2.5 3.5 4.5 5.5 VDLV_ = 0 VDHV_ = 3V
2.0 1.5 1.0 VDUT_ ERROR (mV) 0.5 0 -0.5 -1.0 -1.5 -2.0 -1.5 -0.5 0.5 NORMALIZED AT VDLV_ = 0 1.5 2.5 3.5 4.5 5.5 VDTV_ = 1.5V VDHV_ = 6.5V
2.0
-2.0 6.5 -1.5 -0.5 0.5
NORMALIZED AT VDHV_ = 3V 1.5 2.5 3.5 4.5 5.5 6.5 VDHV_ (V)
6.5
VDTV_ (V)
VDLV_ (V)
DRIVER GAIN vs. TEMPERATURE
MAX9961/62 toc16
DRIVER OFFSET vs. TEMPERATURE
MAX9961/62 toc17
COMPARATOR OFFSET vs. COMMON-MODE VOLTAGE
1.5 1.0 OFFSET (mV) 0.5 0 -0.5 -1.0 VEE = -6.5V VEE = -4.5V VEE = -5.5V
MAX9961/62 toc18
1.0006 1.0005 1.0004 1.0003 1.0002 1.0001 1.0000 0.9999 0.9998 0.9997 0.9996 NORMALIZED AT TJ = +85C
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 NORMALIZED AT TJ = +85C 60 70 80 TEMPERATURE (C) 90
2.0
OFFSET (mV)
GAIN (V/V)
-1.5 -2.0 100
NORMALIZED AT VCM = 1.5V AND VEE = -5.5V -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
60
70
80 TEMPERATURE (C)
90
100
COMMON-MODE VOLTAGE (V)
COMPARATOR RISING-EDGE TIMING VARIATION vs. COMMON-MODE VOLTAGE
MAX9961/62 toc19
COMPARATOR FALLING-EDGE TIMING VARIATION vs. COMMON-MODE VOLTAGE
MAX9961/62 toc20
COMPARATOR TIMING VARIATION vs. OVERDRIVE
MAX9961/62 toc21
200 150 TIMING VARIATION (ps) 100 50 0 -50 VEE = -6.5V -100 -150 NORMALIZED AT VCM = 1.5V AND VEE = -5.25V -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 VEE = -4.5V VEE = -5.5V
150 100 TIMING VARIATION (ps) 50 0 -50 VEE = -6.5V -100 -150 NORMALIZED AT VCM = 1.5V AND VEE = -5.25V -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 VEE = -4.5V VEE = -5.5V
200 150 100 DELAY (ps) 50 0 RISING EDGE -50 NORMALIZED AT OVERDRIVE = 0.5V -100 FALLING EDGE
6.5
6.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OVERDRIVE (V)
COMMON-MODE VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
12
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
Typical Operating Characteristics (continued)
COMPARATOR TRAILING-EDGE TIMING ERROR vs. PULSE WIDTH
MAX9961/62 toc22
COMPARATOR TIMING VARIATION vs. INPUT SLEW RATE, DUT_ RISING
MAX9961/62 toc23
COMPARATOR TIMING VARIATION vs. INPUT SLEW RATE, DUT_ FALLING
30 20 PROPAGATION DELAY (ps) 10 0 -10 -20 -30 -40 -50 -60 -70 2.5
MAX9961/62 toc24
30 20 10 TIMING ERROR (ps) 0 -10 -20 -30 -40 -50 -60 -70 -80 0 5 10 15 20 NORMALIZED AT PW = 12.5ns PERIOD = 25ns HIGH PULSE LOW PULSE
40 30 20 PROPAGATION DELAY (ns) 10 0 -10 -20 -30 -40 -50 -60 -70 NORMALIZED AT SLEW RATE = 1.2V/ns 0.5 1.0 1.5 SLEW RATE (V/ns) 2.0
40
NORMALIZED AT SLEW RATE = 1.2V/ns 0.5 1.0 1.5 SLEW RATE (V/ns) 2.0 2.5
25
PULSE WIDTH (ns)
COMPARATOR DIFFERENTIAL OUTPUT RESPONSE
MAX9961/62 toc25
COMPARATOR RESPONSE vs. HIGH SLEW-RATE OVERDRIVE
MAX9961/62 toc26
COMPARATOR OFFSET vs. TEMPERATURE
0.6 0.4 OFFSET (mV) 0.2 0 -0.2 -0.4
MAX9961/62 toc27
0.8
HIGH-IMPEDANCE MODE
DIGITIZED OUTPUT
VOUT = 50mV/div
0
V = 500mV/div
INPUT
0 INPUT SLEW RATE = 6V/ns t = 2.50ns/div VDUT_ = 0 TO 3V PULSE, VCHV_ = VCLV_ = +1.5V EXTERNAL LOAD = 50 t = 2.50ns/div
-0.6 -0.8 60 65 70 75 NORMALIZED AT TJ = +85C 80 85 90 95 100
TEMPERATURE (C)
CLAMP RESPONSE
MAX9961/62 toc28
ACTIVE-LOAD VOLTAGE vs. CURRENT
MAX9961/62 toc29
ACTIVE-LOAD LINEARITY ERROR IDUT_ vs. VLDH_
VCOM_ = 2.5V VLDL_ = 0 VDUT_ = 0 LINEARITY ERROR (A) 10
MAX9961/62 toc30
3.0 2.0 1.0 IDUT_ (mA) 0 -1.0 -2.0 -3.0
20
VCOM_ = 2.5V VLDH_ = 5V VLDL_ = 5V
VDUT_ = 500mV/div
RISING EDGE
0
FALLING EDGE
-10 0 CALIBRATION POINTS: VLDH_ = 0.5V, 2.5V -20 1.5 2.0 2.5 VDUT_ (V) 3.0 3.5 0.01 0.1 VLDH_ (V) 1 10
t = 5.0ns/div VDUT_ = 0 TO 3V SQUARE WAVE RS = 25 VCPLV_ = -0.1V, VCPHV_ = +3.1V
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13
Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
Typical Operating Characteristics (continued)
ACTIVE-LOAD LINEARITY ERROR IDUT_ vs. VLDL_
15 LINEARITY ERROR (A) 10 5 0 -5 -10 -15 -20 0.01 0.1 VLDL_ (V) 1 10 CALIBRATION POINTS: VLDL_ = 0.5V, 2.5V VCOM_ = 2.5V VLDH_ = 0 VDUT_ = 5V
MAX9961/62 toc31
HIGH-IMPEDANCE LEAKAGE CURRENT vs. DUT_ VOLTAGE
MAX9961/62 toc32
LOW-LEAKAGE CURRENT vs. DUT_ VOLTAGE
8 7 6 VCHV_ = VCLV_ = +6.5V
MAX9961/62 toc33
20
1.0 0.8 0.6 0.4 IDUT_ (A) VLDH_ = VLDL_ = 5.0V
9
0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.5 -0.5 0.5
IDUT_ (nA)
0.2
5 4 3 2 VCHV_ = VCLV_ = +5.0V
VLDH_ = VLDL_ = 0
1 0 -1 5.5 6.5 VCHV_ = VCLV_ < +3.0V -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
1.5
2.5
3.5
4.5
VDUT_ (V)
VDUT_ (V)
CLAMP CURRENT vs. DIFFERENCE VOLTAGE
1100 1000 900 800 700 600 500 400 300 200 100 0 -100 VCPHV_ (V)
MAX9961/62 toc34
CLAMP CURRENT vs. DIFFERENCE VOLTAGE
MAX9961/62 toc35
HIGH-IMPEDANCE-TO-LOW-LEAKAGE TRANSITION
MAX9961/62 toc36
VDUT_ = 3V VCPL_ = 0
0 -100 -200 -300 IDUT_ (A) -400 -500 -600 -700 -800 -900 VDUT_ = 0, VCPHV_ = 3V -1.25 -1.00 -0.75 VCPLV_ (V) -0.50 -0.25 0 -1000 -1.50
IDUT_ = 400nA/div
LOW LEAKAGE TO HIGH IMPEDANCE
IDUT_ (A)
HIGH IMPEDANCE TO LOW LEAKAGE 0
RL = 100k CL = 20pF 0 t = 5s/div t = 0 INDICATES RISING EDGE OF CS
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0
DRIVER REFERENCE INPUT CURRENTS vs. INPUT VOLTAGE
MAX9961/62 toc37
COMPARATOR REFERENCE INPUT CURRENT vs. INPUT VOLTAGE
MAX9961/62 toc38
INPUT CURRENT vs. INPUT VOLTAGE, CPHV_
650 600 550 ICPHV_ (nA) 500 450 400 350 VCPLV_ = -2.2V
MAX9961/62 toc39
1.5 1.4 1.3 INPUT CURRENT (A) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 IDHV_ IDLV_ IDTV_
3.0 VDUT_ = 6.5V 2.5 INPUT CURRENT (nA) 2.0 1.5 1.0 0.5 0 ICLV_ ICHV_
700
300 250
6.5
-1.5 -0.5 0.5
1.5
2.5
3.5
4.5
5.5
6.5
200 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 VCPHV_ (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
14
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load
Typical Operating Characteristics (continued)
INPUT CURRENT vs. INPUT VOLTAGE, CPLV_
MAX9961/62 toc40
MAX9961/MAX9962
LOAD REFERENCE INPUT CURRENTS vs. INPUT VOLTAGE
MAX9961/62 toc41
INPUT CURRENTS vs. INPUT VOLTAGE, COM_
MAX9961/62 toc42
-600 VCPHV_ = 7.2V -650 -700 ICPLV_ (nA) -750 -800 -850 -900 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5
-500 -550 INPUT CURRENT (nA) -600
ILDH_ AND ILDL_
0 -50 -100 ICOM_ (nA) -150 -200 -250 -300
-650 -700 -750 -800
5.5
0
1
2
3
4
5
-1.5
-0.5
0.5
1.5
2.5
3.5
4.5
5.5
VCPLV_ (V)
INPUT VOLTAGE (V)
VCOM_ (V)
SUPPLY CURRENT, ICC vs. VCC
110 100 90 ICC (mA) 80 70 F 60 RL = 10k, CL = 0.5pF, VEE = -5.25V 50 9.5 9.7 9.9 10.1 VCC (V) 10.3 10.5 -200 E
MAX9961/62 toc43
SUPPLY CURRENT, IEE vs. VEE
-130 B A D C -140 -150 IEE (mA) -160 -170 -180 -190 RL = 10k, CL = 0.5pF, VCC = 9.75V -4.5 -5.5 -5.0 VEE (V) A: VDUT_ = VDTV_ = 1.5V, VDHV_ = 3V, VDLV_ = 0, A: VCHV_ = VCLV_ = 0, VCPHV_ = 7.2V, A: VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0 B: SAME AS 'A' EXCEPT VLDH_ = VLDL_ = 5V C: SAME AS 'A' EXCEPT DRIVER DISABLED HIGH-Z AND LOAD ENABLED D: SAME AS 'C' EXCEPT VLDH_ = VLDL_ = 5V E: SAME AS 'A' EXCEPT LOW-LEAKAGE MODE ASSERTED F: SAME AS 'E' EXCEPT VLDH_ = VLDL_ = 5V -6.0 -6.5 C D A B
MAX9961/62 toc44
E F
A: VDUT_ = VDTV_ = 1.5V, VDHV_ = 3V, VDLV_ = 0, A: VCHV_ = VCLV_ = 0, VCPHV_ = 7.2V, A: VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0 B: SAME AS 'A' EXCEPT VLDH_ = VLDL_ = 5V C: SAME AS 'A' EXCEPT DRIVER DISABLED HIGH-Z AND LOAD ENABLED D: SAME AS 'C' EXCEPT VLDH_ = VLDL_ = 5V E: SAME AS 'A' EXCEPT LOW-LEAKAGE MODE ASSERTED F: SAME AS 'E' EXCEPT VLDH_ = VLDL_ = 5V
ICC vs. TEMPERATURE
MAX9961/62 toc45
IEE vs. TEMPERATURE
-172 -174 -176 IEE (mA) -178 -180 -182 VDUT = VDTV_ = 1.5V, VDHV_ = 3V, VDLV_ = 0, VCHV_ = VCLV_ = 0, VCPHV_ = 7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VCC = 9.75V, VEE = -5.25V 60 70 80 90 100 110
MAX9961/62 toc46
100 95 90 ICC (mA) 85 80 75 70 60 70 80 90 100 VDUT = VDTV_ = 1.5V, VDHV_ = 3V, VDLV_ = 0, VCHV_ = VCLV_ = 0, VCPHV_ = 7.2V, VCPLV_ = -2.2V, VLDH_ = VLDL_ = 0, VCC = 9.75V, VEE = -5.25V
-170
-184 -186 -188 110 -190
TEMPERATURE (C)
TEMPERATURE (C)
______________________________________________________________________________________
15
Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
MAX9961 MAX9962
90% 10% DTV_ 90% DLV_ 10% tDTR (a). DRIVE-TO-TERM RISE AND FALL TIME 10% DTV_ 90% DLV_ tTDF (b). TERM-TO-DRIVE RISE AND FALL TIME
tDTF DHV_ 10% 90%
tTDR DHV_
Figure 1. Drive and Term Timing
Pin Description
PIN MAX9961 1 MAX9962 25 NAME TEMP Temperature Monitor Output FUNCTION
2, 9, 12, 14, 2, 9, 12, 14, 17, 24, 35, 17, 24, 35, 45, 46, 60, 45, 46, 66, 80, 81, 91 80, 81, 91 3, 5, 10, 16, 21, 23, 25, 34, 43, 44, 82, 83, 92 4, 11, 15, 22, 33, 41, 42, 66, 84, 85, 93 6 7 8 13 18 19 20 26 27 28 1, 3, 5, 10, 16, 21, 23, 34, 43, 44, 82, 83, 92 4, 11, 15, 22, 33, 41, 42, 60, 84, 85, 93 20 19 18 13 8 7 6 100 99 98
VEE
Negative Power-Supply Input
GND
Ground Connection
VCC
Positive Power-Supply Input
FORCE1 DUT1 SENSE1 GS SENSE2 DUT2 FORCE2 CLV2 CHV2 DLV2
Channel 1 Force Input from External PMU Channel 1 Device-Under-Test Input/Output. Combined I/O for driver, comparator, clamp, and load. Channel 1 Sense Output to External PMU Ground Sense. GS is the ground reference for LDH_ and LDL_. Channel 2 Sense Output to External PMU Channel 2 Device-Under-Test Input/Output. Combined I/O for driver, comparator, clamp, and load. Channel 2 Force Input from External PMU Channel 2 Low Comparator Reference Input Channel 2 High Comparator Reference Input Channel 2 Driver Low Reference Input
16
______________________________________________________________________________________
Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
Pin Description (continued)
PIN MAX9961 29 30 31 32 36 37 38 39 40 47 48 49 50, 76 51 MAX9962 97 96 95 94 90 89 88 87 86 79 78 77 50, 76 75 NAME DTV2 DHV2 CPLV2 CPHV2 NCH2 CH2 VCCO2 NCL2 CL2 COM2 LDL2 LDH2 N.C. TDATA2 FUNCTION Channel 2 Driver Termination Reference Input Channel 2 Driver High Reference Input Channel 2 Low Clamp Reference Input Channel 2 High Clamp Reference Input Channel 2 Comparator High Output. Differential output of channel 2 high comparator. Channel 2 Collector Voltage Input. Voltage for channel 2 comparator output pullup resistors. This is the pullup voltage for the internal termination resistors. Not internally connected on versions without internal termination resistors. Channel 2 Comparator Low Output. Differential output of channel 2 low comparator. Channel 2 Active-Load Commutation-Voltage Reference Input Channel 2 Active-Load Source-Current Reference Input Channel 2 Active-Load Sink-Current Reference Input No Connection. Do not connect. Channel 2 Data Termination Voltage Input. Termination voltage input for the DATA2 and NDATA2 differential inputs. Not internally connected on versions without internal termination resistors. Channel 2 Multiplexer Control Inputs. Differential controls DATA2 and NDATA2 select driver 2's input from DHV2 or DLV2. Drive DATA2 above NDATA2 to select DHV2. Drive NDATA2 above DATA2 to select DLV2. Channel 2 RCV Termination Voltage Input. Termination voltage input for the RCV2 and NRCV2 differential inputs. Not internally connected on versions without internal termination resistors. Channel 2 Multiplexer Control Inputs. Differential controls RCV2 and NRCV2 place channel 2 into receive mode. Drive RCV2 above NRCV2 to place channel 2 into receive mode. Drive NRCV2 above RCV2 to place channel 2 into drive mode. Channel 2 Load-Enable Termination Voltage Input. Termination voltage input for the LDEN2 and NLDEN2 differential inputs. Not internally connected on versions without internal termination resistors. Channel 2 Multiplexer Control Inputs. Differential controls LDEN2 and NLDEN2 enable/disable the active load. Drive LDEN2 above NLDEN2 to enable the channel 2 active load. Drive NLDEN2 above LDEN2 to disable the channel 2 active load. Reset Input. Asynchronous reset input for the serial register. RST is active low and asserts low-leakage mode. At power-up, hold RST low until VCC and VEE have stabilized. Chip-Select Input. Serial port activation input. CS is active low. Single-Ended Logic Threshold. Leave THR unconnected to set the threshold to +1.25V or force THR to a desired threshold voltage. Serial-Clock Input. Clock for serial port. Data Input. Serial port data input.
52 53
74 73
NDATA2 DATA2
54
72
TRCV2
55 56
71 70
NRCV2 RCV2
57
69
TLDEN2
58 59 61 62 63 64 65
68 67 65 64 63 62 61
NLDEN2 LDEN2 RST CS THR SCLK DIN
______________________________________________________________________________________
17
Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
Pin Description (continued)
PIN MAX9961 67 68 MAX9962 59 58 NAME LDEN1 NLDEN1 FUNCTION Channel 1 Multiplexer Control Inputs. Differential controls LDEN1 and NLDEN1 enable/disable the active load. Drive LDEN1 above NLDEN1 to enable the channel 1 active load. Drive NLDEN1 above LDEN1 to disable the channel 1 active load. Channel 1 Load-Enable Termination Voltage Input. Termination voltage input for the LDEN1 and NLDEN1 differential inputs. Not internally connected on versions without internal termination resistors. Channel 1 Multiplexer Control Inputs. Differential controls RCV1 and NRCV1 place channel 1 into receive mode. Drive RCV1 above NRCV1 to place channel 1 into receive mode. Drive NRCV1 above RCV1 to place channel 1 into drive mode. Channel 1 RCV Termination Voltage Input. Termination voltage input for the RCV1 and NRCV1 differential inputs. Not internally connected on versions without internal termination resistors. Channel 1 Multiplexer Control Inputs. Differential controls DATA1 and NDATA1 select driver 1's input from DHV1 or DLV1. Drive DATA1 above NDATA1 to select DHV1. Drive NDATA1 above DATA1 to select DLV1. Channel 1 Data Termination Voltage Input. Termination voltage input for the DATA1 and NDATA1 differential inputs. Not internally connected on versions without internal termination resistors. Channel 1 Active-Load Sink-Current Reference Input Channel 1 Active-Load Source-Current Reference Input Channel 1 Active-Load Commutation-Voltage Reference Input Channel 1 Low Comparator Output. Differential output of channel 1 low comparator. Channel 1 Collector Voltage Input. Voltage for channel 1 comparator output pullup resistors. This is the pullup voltage for the internal termination resistors. Not internally connected on versions without internal termination resistors. Channel 1 High Comparator High Output. Differential output of channel 1 high-side comparator. Channel 1 High Clamp Reference Input Channel 1 Low Clamp Reference Input Channel 1 Driver High Reference Input Channel 1 Driver Termination Reference Input Channel 1 Driver Low Reference Input Channel 1 High Comparator Reference Input Channel 1 Low Comparator Reference Input Exposed Pad. The exposed pad for heat removal is at VEE potential. Connect to VEE or leave isolated.
69
57
TLDEN1
70 71
56 55
RCV1 NRCV1
72
54
TRCV1
73 74
53 52
DATA1 NDATA1
75 77 78 79 86 87 88 89 90 94 95 96 97 98 99 100 --
51 49 48 47 40 39 38 37 36 32 31 30 29 28 27 26 --
TDATA1 LDH1 LDL1 COM1 CL1 NCL1 VCCO1 CH1 NCH1 CPHV1 CPLV1 DHV1 DTV1 DLV1 CHV1 CLV1 PAD
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
Functional Diagram
CH_ MODE BITS CS SCLK DIN RST THR SERIAL INTERFACE LLEAK SC0 SC1 TMSEL LDCAL SERIAL INTERFACE IS COMMON TO BOTH CHANNELS. MODE BITS ARE INDEPENDENTLY LATCHED FOR EACH CHANNEL. VCC VEE TEMP GND
ONE OF TWO IDENTICAL CHANNELS SHOWN 400 DLV_ DHV_ DTV_ FORCE_ MULTIPLEXER SLEW-RATE CONTROL BUFFER 50 DUT_ 10k SC0 SC1 LLEAK SENSE_
OPTIONAL RDATA 2 x 50 TDATA_
DATA_ NDATA_ RCV_ NRCV_
HIGH-Z
TMSEL TRCV_ OPTIONAL RRCV 2 x 50 CPHV_ CLAMPS
CPLV_ CHV_ CH_ NCH_
MAX9961 MAX9962
VCCO_
OPTIONAL RCCO 4 x 50
COMPARATORS
CL_ NCL_ VCC CLV_ LDH_ SINK (HIGH) CURRENT OPTIONAL RLDEN 2 x 50 TLDEN_ LDCAL LLEAK ACTIVELOAD CONTROL ACTIVE LOAD
LDEN_ NLDEN_ COM_ LDL_ GS VEE SOURCE (LOW) CURRENT
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19
Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
Detailed Description
The MAX9961/MAX9962 dual, low-power, high-speed, pin electronics DCL ICs include, for each channel, a three-level pin driver, a dual comparator, variable clamps, and an active load. The driver features a -1.5V to +6.5V operating range and high-speed operation, includes high-impedance and active-termination (3rdlevel drive) modes, and is highly linear even at low voltage swings. The dual comparator provides low dispersion (timing variation) over a wide variety of input conditions. The clamps provide damping of high-speed DUT_ waveforms when the device is configured as a high-impedance receiver. The programmable load supplies up to 2mA of source and sink current. The load facilitates contact/continuity testing and pullup of highoutput-impedance devices. The MAX9961A/MAX9962A provide tight matching of offset for the drivers and the comparators allowing reference levels to be shared across multiple channels in cost-sensitive systems. Use the MAX9961B/MAX9962B for system designs that incorporate independent reference levels for each channel. Optional internal resistors at the high-speed inputs provide compatibility with LVPECL, LVDS, and GTL interfaces. Connect the termination voltage inputs (TDATA_, TRCV_, TLDEN_) to the appropriate voltage for terminating LVPECL, GTL, or other logic. Leave the inputs unconnected for 100 differential LVDS termination. See the Selector Guide for termination options. The comparators provide open-collector outputs, which must be pulled up to collector voltage VCCO. Optional internal resistors provide 50 signal termination and pullup without the need for external components. See the Selector Guide for device termination options. See the Comparators section for termination details. A 3-wire, low-voltage, CMOS-compatible serial interface programs the low-leakage, load calibration, slew rate, and tri-state/terminate operational configurations of the MAX9961/MAX9962.
HIGHSPEED INPUTS
REFERENCE INPUTS DLV_ 0 0 DHV_ DTV_ 1 1 1 SLEW RATE BUFFER 0 0
MAX9961 MAX9962
50 DUT_
DATA_ RCV_ HIGH-Z CPHV_ CLAMPS CPLV_ TMSEL LLEAK SC0 SC1 COMPARATORS AND ACTIVE LOAD MODE 4
Figure 2. Simplified Driver Channel
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load
Output Driver
The driver input is a high-speed multiplexer that selects one of three voltage inputs: DHV_, DLV_, or DTV_. This switching is controlled by high-speed inputs DATA_ and RCV_, and mode-control bit TMSEL (Table 1). A slew-rate circuit controls the slew rate of the buffer input. Select to one of four possible slew rates according to Table 2. The speed of the internal multiplexer sets the 100% driver slew rate (see the Driver LargeSignal Response graph in the Typical Operating Characteristics). DUT_ can be toggled at high speed between the buffer output and high-impedance mode, or it can be placed into low-leakage mode (Figure 2, Table 1). In highimpedance mode the clamps are connected. Highspeed input RCV_ and mode control bits TMSEL and LLEAK control the switching. In high-impedance mode, the bias current at DUT_ is less than 1.5A over the 0 to 3V range, while the node maintains its ability to track high-speed signals. In low-leakage mode, the bias current at DUT_ is further reduced to less than 15nA, and signal tracking slows. See the Low-Leakage Mode section for more details. The nominal driver output resistance is 50. Contact the factory for different resistance values within the 45 to 51 range.
Table 1. Driver Logic
EXTERNAL CONNECTIONS DATA_ 1 0 X X X RCV_ 0 0 1 1 X INTERNAL CONTROL REGISTER TMSEL X X 1 0 X LLEAK 0 0 0 0 1 Drive to DHV_ Drive to DLV_ Drive to DTV_ (term mode) High-impedance mode (high-z) Low-leakage mode
MAX9961/MAX9962
DRIVER OUTPUT
Table 2. Slew Rate Logic
SC1 0 0 1 1 SC0 0 1 0 1 DRIVER SLEW RATE (%) 100 75 50 25
Clamps
Configure the voltage clamps (high and low) to limit the voltage at DUT_ and to suppress reflections when the channel is configured as a high-impedance receiver. The clamps behave as diodes connected to the outputs of high-current buffers. Internal circuitry compensates for the diode drop at 1mA clamp current. Set the clamp voltages using the external connections CPHV_ and CPLV_. The clamps are enabled only when the driver is in the high-impedance mode (Figure 2). For transient suppression, set the clamp voltages to approximately the minimum and maximum expected DUT_ voltage range. The optimal clamp voltages are application specific and must be empirically determined. If clamping is not desired, set the clamp voltages at least 0.7V outside the expected DUT_ voltage range; overvoltage protection remains active without loading DUT_.
Table 3. Comparator Logic
DUT_ > CHV_ 0 0 1 1 DUT_ > CLV_ 0 1 0 1 CH_ 0 0 1 1 CL_ 0 1 0 1
Comparators
The MAX9961/MAX9962 provide two independent highspeed comparators for each channel. Each comparator has one input connected internally to DUT_ and the other input connected to either CHV_ or CLV_ (see the Functional Diagram). Comparator outputs are a logical result of the input conditions, as indicated in Table 3.
The comparator differential outputs are open collector. This configuration switches an 8mA current source between the two outputs, and is available with and without internal termination resistors connected to V CCO_ (Figure 3). For external termination, leave VCCO_ unconnected and add the required external resistors. These resistors are typically 50 to the pullup voltage at the receiving end of the output trace. Alternate configurations to terminate different path impedances can be used provided that the Absolute Maximum Ratings are not exceeded. Note that the resistor value also sets the voltage swing. For internal termination, connect VCCO_ to the desired VOH voltage. The output provides a nominal 400mVP-P swing and 50 source termination.
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21
Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
Table 4. Active Load Programming
MAX9961 MAX9962
DUT_ CH_
EXTERNAL CONNECTIONS LDEN_ 0 1
INTERNAL CONTROL REGISTER LDCAL LLEAK 0 0 1 X 0 0 0 1
MODE
CHV_
NCH_
Normal operating mode, load disabled Normal operating mode, load enabled Load enabled for diagnostics Low-leakage mode
8mA OPTIONAL 4 x 50 VEE 8mA
VCCO_
X X
CL_
CLV_
NCL_
Figure 3. Open-Collector Comparator Outputs
Active Load
The active load consists of linearly programmable source and sink current sources, a commutation buffer, and a diode bridge (see the Functional Diagram). Analog control inputs LDH_ and LDL_ program the sink and source currents, respectively, within the 0 to 2mA range. Analog reference input COM_ sets the commutation buffer output voltage. The source and sink naming convention is referenced to the device under test. Current out of the MAX9961/MAX9962 constitutes sink current while current into the MAX9961/MAX9962 constitutes source current. The programmed source (low) current loads the device under test when VDUT_ > VCOM_. The programmed sink (high) current loads the device under test when VDUT_ < VCOM_. The GS input allows a single level-setting DAC, such as the MAX5631 or MAX5734, to program the MAX9961/
MAX9962s' active load, driver, comparator, and clamps. Although all the DAC levels typically are offset by V GS , the operation of the MAX9961/MAX9962s' ground-sense input nullifies this offset with respect to the active-load currents. Connect GS to the ground reference used by the DAC. (VLDL_ - VGS) sets the source current by +400A/V. (VLDH_ - VGS) sets the sink current by -400A/V. The high-speed differential input LDEN_ and 2 bits of the control word, LDCAL and LLEAK, control the load (Table 4). When the load is enabled, the internal source and sink current sources connect to the diode bridge. When the load is disabled, the internal current sources shunt to ground and the top and bottom of the bridge float (see the Functional Diagram). LLEAK places the load into low-leakage mode. LLEAK overrides LDEN_ and LDCAL. See the Low-Leakage Mode section for more detailed information. Load Calibration Enable, LDCAL The LDCAL signal enables the load independently of the state of LDEN_. In some tester configurations, the load enable is driven with the complement of the driver high-impedance signal (RCV_), so disabling the driver enables the load and vice versa. LDCAL allows the load and driver to be simultaneously enabled for diagnostic purposes in this tester configuration (Table 4).
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
tCH SCLK tCSS0 tCL tCSH1 tCSS1
CS tCSWH
tDH tDS DIN D6 D5 D4 D3 D2 D1 D0
Figure 4. Serial Interface Timing
Low-Leakage Mode, LLEAK Asserting LLEAK through the serial port or with RST places the MAX9961/MAX9962 into a very-low-leakage state (see Electrical Characteristics). The comparators function at full speed, but the driver, clamps, and active load are disabled. This mode is convenient for making IDDQ and PMU measurements without the need for an output disconnect relay. LLEAK is independent for each channel. When DUT_ is driven with a high-speed signal while LLEAK is asserted, the leakage current momentarily increases beyond the limits specified for normal operation. The low-leakage recovery specification in the Electrical Characteristics table indicates device behavior under this condition.
SCLK
MAX9961 MAX9962
SHIFT REGISTER
DIN 0 CS ENABLE 1 2 3 4 5 6
F/F 4 6 D ENABLE SET RST Q 4 5 D
F/F Q
ENABLE SET
Serial Interface and Device Control
A CMOS-compatible serial interface controls the MAX9961/MAX9962 modes (Figure 5). Control data flow into a 7-bit shift register (MSB first) and are latched when CS is taken high, as shown in Figure 4. Data from the shift register are then loaded to either or both of the latches as determined by bits D5 and D6, and indicated in Figure 5 and Table 5. The latches contain the 5 mode bits for each channel of the dual-pin driver. The mode bits, in conjunction with external inputs DATA_ and RCV_, manage the features of each channel, as shown in Figure 2 and Tables 1 and 2. RST sets LLEAK = 1 for both channels, forcing them into low-leakage mode. At powerup, hold RST low until VCC and VEE have stabilized.
F/F 0-3 6 D ENABLE Q 4 1 0-3 5 D
F/F Q 4 1
ENABLE
20k THR VTHRINT = 1.25V LDCAL, LLEAK TMSEL, SC0, SC1 LDCAL, LLEAK TMSEL, SC0, SC1 CHANNEL 2 MODE BITS
CHANNEL 1 MODE BITS
Figure 5. Serial Interface ______________________________________________________________________________________ 23
Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
Table 5. Shift Register Functions
BIT D6 NAME CH1 DESCRIPTION Channel 1 Write Enable. Set to 1 to update the control byte for channel 1. Set to 0 to make no changes to channel 1. Channel 2 Write Enable. Set to 1 to update the control byte for channel 2. Set to 0 to make no changes to channel 2. Low-Leakage Select. Set to 1 to put driver, load, and clamps into low-leakage mode. Comparators remain active in low-leakage mode. Set to 0 for normal operation.
Analog control input THR sets the threshold for the input logic, allowing operation with CMOS logic as low as 0.9V. Leaving THR unconnected results in a nominal threshold of 1.25V from an internal reference, providing compatibility with 2.5V to 3.3V logic.
Temperature Monitor
The MAX9961/MAX9962 supply a temperature output signal, TEMP, that asserts a nominal output voltage of 3.43V at a die temperature of +70C (343K). The output voltage increases with temperature at 10mV/C.
D5
CH2
D4
LLEAK
Heat Removal
Under normal circumstances, the MAX9961/MAX9962 require heat removal through the exposed pad by use of an external heat sink. The exposed pad is electrically at VEE potential, and must be either connected to VEE or isolated. The pad is located on the top of the MAX9961, and on the bottom of the MAX9962.
D3
Termination Select. Driver termination select bit. Set to 1 to force the driver output to the DTV_ voltage (term mode) when RCV_ = 1. TMSEL Set to 0 to place the driver into highimpedance mode (high-Z) when RCV_ = 1. See Table 1. SC1 SC0 Driver Slew Rate Select. SC1 and SC0 set the driver slew rate. See Table 2.
D2 D1 D0
Load Calibrate. Overrides LDEN to enable load. LDCAL Set LDCAL to 1 to enable load. Set LDCAL to 0 for normal operation. See Table 4.
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
Typical Application Circuits (Simplified)
RB - RE
RCOM REFERENCE IN INPUT MAIN AMP
RXA
RXD
SENSE
FORCE
FORCE 10k DUT ~45
DHV DTV DLV CURRENTSENSE AMP
400
MSR TO ADC
SENSE
PMU MAX9949 MAX9950
REFERENCE INPUTS
DCL MAX9961 MAX9962
DRIVER IN LOW-LEAKAGE MODE
INTERFACING TO PMU WITHOUT EXTERNAL RELAYS. PMU SOURCING 2mA OR LESS.
RB - RE
RCOM REFERENCE IN INPUT MAIN AMP
RXA
RXD
SENSE
FORCE
FORCE 10k DUT ~45
DHV DTV DLV CURRENTSENSE AMP
400
MSR TO ADC
SENSE
PMU MAX9949 MAX9950
REFERENCE INPUTS
DCL MAX9961 MAX9962
DRIVER = DTV
INTERFACING TO PMU WITHOUT EXTERNAL RELAYS. DCL SOURCING UP TO 60mA.
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25
Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
Selector Guide
PART MAX9961ADCCQ MAX9961AGCCQ MAX9961ALCCQ MAX9961BDCCQ MAX9961BGCCQ MAX9961BLCCQ MAX9962ADCCQ MAX9962AGCCQ MAX9962ALCCQ MAX9962BDCCQ MAX9962BGCCQ MAX9962BLCCQ ACCURACY GRADE A A A B B B A A A B B B COMPARATOR OUTPUT TERMINATION None None 50 to VCCO_ None None 50 to VCCO_ None None 50 to VCCO_ None None 50 to VCCO_ HIGH-SPEED DIGITAL INPUT TERMINATION None 100 with center tap 100 with center tap None 100 with center tap 100 with center tap None 100 with center tap 100 with center tap None 100 with center tap 100 with center tap HEAT EXTRACTION Top Top Top Top Top Top Bottom Bottom Bottom Bottom Bottom Bottom
Chip Information
TRANSISTOR COUNT: 5130 PROCESS: Bipolar EXPOSED PAD: At VEE potential; connect to VEE or leave isolated.
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages.
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Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load
Pin Configurations
TOP VIEW
CPHV1 CPLV1 COM1 VCCO1 NCH1 CHV1 DHV1 NCL1 LDH1 CLV1 DLV1 DTV1 LDL1 GND GND GND CH1 N.C. CL1 VCC VCC VCC VEE VEE VEE
MAX9961/MAX9962
100 TEMP VEE GND VCC GND FORCE1 DUT1 SENSE1 VEE GND VCC VEE GS VEE VCC GND VEE SENSE2 DUT2 FORCE2 GND VCC GND VEE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 CLV2
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76 75 74 73 72 71 70 69 68 67 66 65 64 TDATA1 NDATA1 DATA1 TRCV1 NRCV1 RCV1 TLDEN1 NLDEN1 LDEN1 VCC DIN SCLK THR CS RST VEE LDEN2 NLDEN2 TLDEN2 RCV2 NRCV2 TRCV2 DATA2 NDATA2 TDATA2
MAX9961
63 62 61 60 59 58 57 56 55 54 53 52 51
27 CHV2
28 DLV2
29 DTV2
30 DHV2
31 CPLV2
32 CPHV2
33 VCC
34 GND
35 VEE
36 NCH2
37 CH2
38 VCCO2
39 NCL2
40 CL2
41 VCC
42 VCC
43 GND
44 GND
45 VEE
46 VEE
47 COM2
48 LDL2
49 LDH2
50 N.C.
TQFP-EPR
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27
Dual, Low-Power, 500Mbps ATE Drivers/Comparators with 2mA Load MAX9961/MAX9962
Pin Configurations (continued)
TOP VIEW
CPHV2 CPLV2 COM2 VCCO2 NCH2 CHV2 DHV2 NCL2 LDH2 77 CLV2 DLV2 DTV2 LDL2 GND GND GND CH2 N.C. 76 75 74 73 72 71 70 69 68 67 66 65 64 TDATA2 NDATA2 DATA2 TRCV2 NRCV2 RCV2 TLDEN2 NLDEN2 LDEN2 VEE RST CS THR SCLK DIN VCC LDEN1 NLDEN1 TLDEN1 RCV1 NRCV1 TRCV1 DATA1 NDATA1 TDATA1 63 62 61 60 59 58 57 56 55 54 53 52 51 26 CLV1 27 CHV1 28 DLV1 29 DTV1 30 DHV1 31 CPLV1 32 CPHV1 33 VCC 34 GND 35 VEE 36 NCH1 37 CH1 38 VCCO1 39 NCL1 40 CL1 41 VCC 42 VCC 43 GND 44 GND 45 VEE 46 VEE 47 COM1 48 LDL1 49 LDH1 50 N.C. CL2 VCC VCC VCC VEE VEE 81 VEE 80
100 GND VEE GND VCC GND FORCE2 DUT2 SENSE2 VEE GND VCC VEE GS VEE VCC GND VEE SENSE1 DUT1 FORCE1 GND VCC GND VEE TEMP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
79
78
MAX9962
TQFP-EP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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